DocumentCode :
3387038
Title :
A novel double RESURF LDMOS with optimized ESD robustness
Author :
Jiang, Lingli ; Qiao, Ming ; Li, Zhaoji ; Zhang, Bo
Author_Institution :
Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fYear :
2009
fDate :
23-25 July 2009
Firstpage :
638
Lastpage :
640
Abstract :
In this paper, a double RESURF LDMOS with optimized ESD robustness is proposed. By implanting P+ at the drain region, an additional discharge path through a vertical PNP is formed. The current density at the source side is reduced, thus it restrains the triggering of the parasitic lateral NPN. The discharge limits under ESD stress of this structure is altered from the triggering of the parasitic lateral NPN to the second breakdown of the parasitic vertical PNP. Contrast to the conventional structure, the discharge ability of the novel device increases form 1.57times10-5 Amum-1 to 3.13times10-5 Amum-1.
Keywords :
MOS integrated circuits; electrostatic discharge; current density; double RESURF LDMOS; electrostatic discharge protection devices; lateral double-diffusion MOS transistor; optimized ESD robustness; parasitic lateral NPN; parasitic vertical PNP; vertical PNP; Breakdown voltage; Current density; Electric breakdown; Electrostatic discharge; Fault location; Immune system; Medical simulation; Robustness; Stress; Thyristors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Circuits and Systems, 2009. ICCCAS 2009. International Conference on
Conference_Location :
Milpitas, CA
Print_ISBN :
978-1-4244-4886-9
Electronic_ISBN :
978-1-4244-4888-3
Type :
conf
DOI :
10.1109/ICCCAS.2009.5250431
Filename :
5250431
Link To Document :
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