Optimizing performance of Super-Lattice Castellated Field Effect Transistors

High performance RF switch components are vital for the successful implementation of a variety of system architectures, ranging from phased array radars and multi-function sensors to the wireless components of mobile phones and consumer electronics. FET based RF switches offer low power consumption, less demanding control biasing networks and fast switching capabilities compared to both PiN and RF MEMS technologies. However, many of these switch technologies, including those based on Si CMOS [1], GaAs pHEMT [2], or InP [3] and GaN HEMTs [4] have reported substantially higher insertion losses than the PiN diode and RF MEMS technologies. With this in mind, Northrop Grumman has recently introduced a novel field effect transistor structure called the Super-Lattice Castellated Field Effect Transistor, or SLCFET, that combines the advantages of FET-based switches with the performance of MEMS [5]. However, this is a new transistor structure that creates challenges for device design, especially with regard to managing electric fields for high breakdown voltage. This paper will discuss some of the challenges, tradeoffs, and techniques for optimizing the SLCFET device performance.