Five-level five-phase PWM signal generation using FPGA

This paper presents a method and implementation of sinusoidal PWM waveform generation for a five-phase five-level converter using FPGA technology. Multilevel converters have the advantage of higher power rating and lower harmonic distortion. The disadvantage is the increased number of switches which need to operate in parallel. FPGAs are the ideal choice in these applications as they offer massive parallelism besides being field-programmable. The algorithm presented in this paper uses relatively few logic elements with no complex mathematical operations that can be implemented in simple low cost FPGAs. The algorithm is implemented in Verilog HDL language and simulated with Quartus II software. Finally, the compiled program is tested using Altera DE2 board that uses Cyclone II FPGA device.