Title :
Functional timing optimization
Author_Institution :
Cadence Berkeley Labs., USA
Abstract :
It is widely believed that any true (or sensitizable) critical path of length /spl ges/2 T must be speeded up in order for a circuit to have a delay \n\n\t\t
Keywords :
circuit optimisation; delays; logic CAD; timing; circuit delay; critical path; delay assignments; functional timing optimization; logic circuit; Circuit analysis; Laboratories; Logic circuits; Propagation delay; Sufficient conditions; Timing;
Conference_Titel :
Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-5832-5
DOI :
10.1109/ICCAD.1999.810708
