Estimation of maximum switching activity in digital VLSI circuits

Author

Bobba, S. ; Hajj, I.N.

Author_Institution

Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA

Volume

2

fYear

1997

fDate

3-6 Aug. 1997

Firstpage

1130

Abstract

Power dissipation and reliability are important issues in the design of high performance digital VLSI circuits. Power dissipation and reliability are strongly related to switching activity in the circuit. An estimate of maximum switching activity is necessary for the design of reliable circuits. The problem of estimating maximum switching activity even under a zero gate delay model is intractable. In this paper, we present an algorithm to obtain an upper bound on the maximum transition count over all possible input vectors under a zero gate delay model.

Keywords

CMOS digital integrated circuits; VLSI; circuit analysis computing; delays; graph theory; integrated circuit reliability; CMOS circuits; digital VLSI circuits; input vectors; maximum switching activity estimation; maximum transition count; power dissipation; reliability; upper bound; zero gate delay model; CMOS logic circuits; Delay estimation; Integrated circuit reliability; Logic circuits; Monte Carlo methods; Power dissipation; Switches; Switching circuits; Upper bound; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on

Print_ISBN

0-7803-3694-1

Type

conf

DOI

10.1109/MWSCAS.1997.662276

Filename

662276