Circuit partitioning for low power BIST design with minimized peak power consumption

In this paper, we propose a novel low power/energy built-in self test (BIST) strategy based on circuit partitioning. The goal of the proposed strategy is to minimize the average power, the peak power and the energy consumption during pseudo-random testing without modifying the fault coverage. The strategy consists in partitioning the original circuit into two structural subcircuits so that each subcircuit can be successively tested through two different BIST sessions. In partitioning the circuit and planning the test session, the switching activity in a time interval (i.e. the average power) as well as the peak power consumption are minimized. Moreover, the total energy consumption during BIST is also reduced since the test length required to test the two subcircuits is roughly the same as the test length for the original circuit. Results on ISCAS circuits show that average power reduction of up to 72%, peak power reduction of up to 53%, and energy reduction of up to 84% can be achieved