DocumentCode
3389151
Title
Fault simulation techniques to reduce IDDQ measurement vectors for sequential circuits
Author
Higami, Yoshinobu ; Takamatsu, Yuzo ; Saluja, Kewal K. ; Kinoshita, Kozo
Author_Institution
Ehime Univ., Matsuyama, Japan
fYear
1999
fDate
1999
Firstpage
141
Lastpage
146
Abstract
This paper presents fault simulation techniques for selecting a small number of IDDQ measurement vectors from a given test sequence while maintaining the original fault coverage. The proposed method covers a class of bridging faults and uses parallel fault simulation wherever possible. Experimental results are presented to demonstrate the effectiveness of the proposed method
Keywords
CMOS logic circuits; electric current measurement; fault simulation; integrated circuit testing; logic simulation; logic testing; sequential circuits; vectors; CMOS circuits; IDDQ measurement vector reduction; bridging faults; fault coverage; fault simulation techniques; logic simulation; parallel fault simulation; sequential circuits; test sequence; Circuit faults; Circuit simulation; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian
Conference_Location
Shanghai
ISSN
1081-7735
Print_ISBN
0-7695-0315-2
Type
conf
DOI
10.1109/ATS.1999.810742
Filename
810742
Link To Document