A practical scheduling architecture and its implementation for Input-Queued Switches

To increase both the capacity and the processing speed for input-queued (IQ) switches, a fair scalable scheduling architecture (FSSA) has been proposed. By employing FSSA comprised of several chips of cascaded sub-scheduler, a large-scale high performance network scheduler can be realized without the capacity limitation of monolithic device. In this paper, we present an improved scheduling algorithm named FSSA_DI instead of the ordinary FSSA. Using the proposed algorithm where a distributed iteration scheme is employed, the scheduler performance can be improved and the processing time can be reduced as well. Simulation results show that FSSA_DI achieves better performance on average delay and throughput under heavy loads compared to other existing algorithms. Moreover, a practical 64 times 64 FSSA using FSSA_DI algorithm is implemented with 4 Xilinx Vertex-4 FPGAs. Measurement results show that the data rates of our solution can be up to 800 Mbps and the tradeoff between performance and hardware complexity has been solved peacefully.