Application of segmented auto threshold (SAT) for 0.5 μm and 0.35 μm logic interconnect layers

In semiconductor processing, the chemical mechanical polishing technique (CMP) for planarising the inter-level dielectric layer has become a common practice. Unfortunately, the polishing causes a smooth oxide thickness variation across the wafer which appears as colour variation when inspected by a bright field inspection system. The CMP process is usually followed by a Contact or Via operation filled with Tungsten Plug and then by a metallisation scheme. The metal is typically deposited at a temperature of about 450 °C which results in a grainy metal