• DocumentCode
    3389794
  • Title

    Memory property of APTMS-mediated Au-SiO2 core-shell nanocrystal memory

  • Author

    Sheng-Fu Huang ; An-Ching Hsiao ; Fu-Ken Liu ; Ching-Chich Leu

  • Author_Institution
    Dept. of Chem. & Mater. Eng., Nat. Univ. of Kaohsiung, Kaohsiung, Taiwan
  • fYear
    2013
  • fDate
    2-4 Jan. 2013
  • Firstpage
    185
  • Lastpage
    186
  • Abstract
    Conventional flash memory, utilizing floating gate as charge storage nodes, had met the leakage challenges as the devices tend to be scaling down and have high densities. Nanocrystal (NC) floating gate memory devices, containing nanocrystals as the discrete charge traps, have attracted attention as strong candidates to act as nonvolatile memories devices due to their scalability, electrical isolation and low charge leakage through the tunneling oxide. In this work, an all-solution processed MOS memory structure containing colloidal Au NPs within a sol-gel derived HfO2 oxide layer was fabricated. We use chemical reduction method to synthesize Au nanoparticles, and use the 3-aminopropyltrimethoxysilane (APTMS) to make the nanoparticles being self-assembled on SiO2 oxide layer. Finally, it is covered by sol-gel derived Hf02 as a control oxide to construct a NC memory structure. To improve the memory device property, we use a simple but effective SAM method to construct an Au-SiO2 core-shell NC capacitor by means of APTMS as a mediator. The Au-SiO2 core-shell structure was constructed by a two-run APTMS SAM process which was conducted before and after the SAM of the colloidal Au NPs. The first-run APTMS formed a well-organized monolayer on substrate which was responsible for capturing the high-density of the Au NPs. Next, the second-run APTMS formed an APTMS bilayer around the Au NPs. A following 500 °C-annealing completed the Au-SiO2 core-shell structure within the HfO2 layer to form a Si/SiO2/Au-SiO2 core-shell/HfO2 floating structure. The effects of APTMS-mediated SiO2 shell on the property of memory device were investigated.
  • Keywords
    annealing; electron traps; flash memories; gold; hafnium compounds; nanoelectronics; nanoparticles; random-access storage; self-assembly; silicon; silicon compounds; sol-gel processing; 3-aminopropyltrimethoxysilane; APTMS bilayer; APTMS-mediated core-shell nanocrystal memory; MOS memory; SAM method; Si-SiO2-Au-SiO2-HfO2; annealing; charge storage nodes; chemical reduction method; discrete charge traps; flash memory; memory property; nanocrystal floating gate memory devices; nanoparticles; nonvolatile memories; self-assembly; sol-gel processing; temperature 500 degC; tunneling oxide; well-organized monolayer; Conferences; DVD; Decision support systems; Nanoelectronics;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nanoelectronics Conference (INEC), 2013 IEEE 5th International
  • Conference_Location
    Singapore
  • ISSN
    2159-3523
  • Print_ISBN
    978-1-4673-4840-9
  • Electronic_ISBN
    2159-3523
  • Type

    conf

  • DOI
    10.1109/INEC.2013.6465992
  • Filename
    6465992