Testing the logic cells and interconnect resources for FPGAs

Author

Doumar, Abderrahim ; Ito, Hideo

Author_Institution

Dept. of Inf. & Comput. Sci., Chiba Univ., Japan

fYear

1999

fDate

1999

Firstpage

369

Lastpage

374

Abstract

This paper presents a new design for testing SRAM based field programmable gate arrays (FPGAs). The new proposed method is able to test both the configurable logic blocks (CLBs) and the interconnection networks. The proposed design is based on slightly modifying the original SRAM part in the FPGA so that it will allow the configuration data to be looped on a chip and then the test becomes easier. This method requires a very short test time compared to the previous works. Moreover, the off-chip memory used in the storage of the configurations data is considerably reduced. The application of this method to the XC4000 family and ORCA shows that (relative to that required by the previous works) the test time can be reduced by 87.2% and the required off-chip memory can be reduced by 88.6%

Keywords

fault simulation; field programmable gate arrays; integrated circuit interconnections; integrated circuit testing; logic design; logic testing; FPGA testing; ORCA FPGA; SRAM-based FPGA; XC4000 FPGA family; configurable logic blocks; configuration data; field programmable gate arrays; interconnect resources; interconnection networks; logic cells; offchip memory reduction; test time reduction; Field programmable gate arrays; Logic testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1999. (ATS '99) Proceedings. Eighth Asian

Conference_Location

Shanghai

ISSN

1081-7735

Print_ISBN

0-7695-0315-2

Type

conf

DOI

10.1109/ATS.1999.810777

Filename

810777