A low power ultra-wideband CMOS LNA for 3.1–10.6-GHz wireless receivers

A CMOS 3.1-10.6GHz low power low noise amplifier utilizing a feedback technique is presented. The shunt and series-inductive peaking techniques have been used in the input and output stages to extend the 3-dB bandwidth of the LNA. To achieve wide and stable power and noise matching, the frequency dependent Miller multiplication factors, combined with a newly added parallel input inductor, is employed. The design is implemented in standard 0.13μm CMOS process. The LNA dissipates only 5.2mW power from 1.2V supply voltage while it achieves a maximum power gain of 7.5dB, input return loss of better than -7.5dB, and minimum noise figure of 6.3 dB over the band of interest. The very small power consumption of this design makes it ideal for RFID applications. The chip area is only 700×1000μm including all test pads and ESD protection.