Title :
Analog front-end for a 3 Gb/s POF receiver
Author :
Dong, Yunzhi ; Martin, Ken
Author_Institution :
Deptartment of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
fDate :
May 30 2010-June 2 2010
Abstract :
This paper describes a receiver front-end that is designed to realize multi-gigabit data communication via large-core plastic optical fiber (POF) in deep submicron CMOS technology. A 3D system-level integration scheme and transistor level circuits have been proposed for such a low-cost, high-speed POF receiver. With 44 mW (excluding output driver) DC power dissipated from a 1.2 V supply and an estimated 13 pF photo capacitance (CPD) from a discrete, large-area (400 um) photo detector (PD), a data rate of 3 Gbps, with a sensitivity of -11 dBm (BER = 10-12), has been simulated in STMicroelectronics (STM) 65 nm low-power CMOS technology.
Keywords :
CMOS integrated circuits; data communication; integration; optical fibre communication; optical receivers; 3D system-level integration scheme; STMicroelectronics; analog front-end; bit rate 3 Gbit/s; capacitance 13 pF; deep submicron CMOS technology; large-core plastic optical fiber receiver; loss 11 dB; multigigabit data communication; photo detector; power 44 mW; receiver front-end; transistor level circuits; voltage 1.2 V; Bit error rate; CMOS technology; Capacitance; Data communication; Detectors; Driver circuits; Optical design; Optical fibers; Optical receivers; Plastics;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537977
