A scalable and fault-tolerant routing algorithm for NoCs

Computing design has been moving to multi-core or many-core domain and Network-on-chip (NoC) is upcoming. However, manufacturing defects and hard malfunction are inevitable, and fault-tolerant routing algorithm is important to provide the required communication in spite of failures. The proposed algorithm, referred to as scalable and fault-tolerant distributed routing (SFDR), partitions the system into nine regions using the concept of divide-and-conquer. Each region guarantees fault-tolerance of one´s own area and the whole system still works no matter where the fault node locates. The novel routing algorithm has excellent scalability with hardware cost keeping constant independent of system size. The router has been synthesized using SMIC 0.13um CMOS process and there is almost no hardware overhead compared to Logic-Based Distributed Routing (LBDR) which is only partially fault-tolerant and hardware cost reduces up to 42% compared to table-based routing.