A CMOS robust fully-balanced-signal generator

In this paper a new single-ended-input fully-balanced-output circuit (SFC) is proposed as an input interface for fully balanced signal processing systems. The new SFC can overcome the drawback of uncontrollable process variation of resistors and generate well-controlled process invariant common mode output voltage, V_{0, com}. The adopted active current common mode feedback compensation makes this possible. Simulations have been carried out using MOSIS 2 μm N-well process and a 3 V supply, showing that with ±100% variation of resistor V_{0, com} only varies by less than ±2%. In addition, it is shown that V_{0, com} is accurately controlled by a preset DC voltage.