Simultaneous subthreshold and gate-oxide tunneling leakage current analysis in nanometer CMOS design

Author

Lee, Dongwoo ; Kwong, Wesley ; Blaauw, David ; Sylvester, Dennis

Author_Institution

Michigan Univ., Ann Arbor, MI, USA

fYear

2003

fDate

24-26 March 2003

Firstpage

287

Lastpage

292

Abstract

In this paper we develop a fast approach to analyze the total leakage power of a large circuit block, considering both gate leakage, I_gate, and subthreshold leakage, I_sub. The interaction between I_sub and I_gate complicates analysis in arbitrary CMOS topologies. We propose simple and accurate heuristics to quickly estimate the state-dependent total leakage current considering the interaction between I_sub and I_gate. We apply this method to ISCAS benchmark circuits in a projected 100 nm technology and demonstrate excellent accuracy compared to SPICE simulation with a 20,000X speedup on average.

Keywords

CMOS digital integrated circuits; integrated circuit design; integrated circuit modelling; leakage currents; nanoelectronics; tunnelling; ISCAS benchmark circuits; SPICE simulation; arbitrary CMOS topologies; circuit block; gate leakage; gate oxide tunneling leakage current analysis; heuristics; leakage power; nanometer CMOS design; state dependent total leakage current; subthreshold leakage; Circuits; Curve fitting; Gate leakage; Leakage current; Minimization; Nonlinear equations; Predictive models; Semiconductor device modeling; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on

Print_ISBN

0-7695-1881-8

Type

conf

DOI

10.1109/ISQED.2003.1194747

Filename

1194747