A study of 90nm MOSFET subthreshold hump characteristics using newly developed MOSFET array test structure

Author

Mizumura, A. ; Ohishi, T. ; Yokoyama, N. ; Nonaka, M. ; Tanaka, S. ; Ammo, H.

Author_Institution

Semicond. Technol. Dev. Group, Sony Corp., Kanagawa, Japan

fYear

2005

fDate

4-7 April 2005

Firstpage

39

Lastpage

42

Abstract

In this paper, 90 nm MOSFET subthreshold hump characteristics are reported for the first time by using a newly developed MOSFET array test structure, which has small-scale DUTs with a new layout pattern, in order to eliminate the influence of gate leakage and off leakage on measured MOSFET parameter data such as Vth, Ion, subthreshold slope, etc. It is confirmed that a subthreshold hump occurs at random in an array, and the hump occurrence percentage differs with chips in a wafer. By extracting the hump variation with a MOSFET array, it is possible to estimate accurately and reduce the standby-current in logic LSI chips.

Keywords

MOSFET; leakage currents; semiconductor device testing; 90 nm; MOSFET array hump variation; MOSFET array test structure; MOSFET subthreshold hump characteristics; early process definition; gate leakage; hump occurrence percentage; logic LSI chips; off leakage; production yield enhancement; small-scale DUT layout pattern; standby-current; subthreshold slope; Circuit testing; Fluctuations; Gate leakage; Isolation technology; Large-scale systems; Logic arrays; MOSFET circuits; Semiconductor device measurement; Subthreshold current; Time measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2005. ICMTS 2005. Proceedings of the 2005 International Conference on

Print_ISBN

0-7803-8855-0

Type

conf

DOI

10.1109/ICMTS.2005.1452215

Filename

1452215