Fast median filtering algorithm based on FPGA

Median filter has good capabilities for reducing a variety kind of random noise, and causes less ambiguity than linear smoothing filters under same processing size. In order to suppress the impulse noise of digital video signal and meet the system´s needs of real-time, it is of great significance to do fast filtering of image based on hardware. By analyzing the common 3×3 filtering window´s mathematical model, this paper proposes a fast median filtering algorithm based on field programmable gate array (FPGA) and the scheme design. According to the characteristics of parallel structures and its suitable for pipeline design of FPGA. VHDL and schematic design are used in this paper to design the implement circuit. Quartus II is used for timing simulation. The results show that it can filter the impulse noise in real time and improves the quality of image.