• DocumentCode
    3395837
  • Title

    NoC architecture with local bus design for network coding

  • Author

    Hu Jian-hao ; Zhang Si-wei

  • Author_Institution
    Nat. Key Lab. of Scie. & Tech. on Commun., Univ. of Electron. Scie. & Tech. of China, Chengdu, China
  • fYear
    2011
  • fDate
    17-19 Aug. 2011
  • Firstpage
    1151
  • Lastpage
    1154
  • Abstract
    A novel Network on Chip (NoC) architecture based on local bus to achieve high efficient multicast and broadcast data transmission is proposed in this paper. The Network Coding (NC) is adopted in the proposed architecture. Compared with the traditional NoC design, the proposed NoC architecture can improve the data throughput and decrease the hardware complexity. In the proposed architecture the process elements are connected with the logical network, which is established with interconnected local mono-direction buses. The proposed architecture inherits the advantages both bus and traditional NoC, and provides the possibility for NC. From the analysis and case studies, we find that the proposed architecture can enhance the performance of NoC with NC.
  • Keywords
    network coding; network-on-chip; telecommunication network reliability; NoC architecture; broadcast data transmission; data throughput; hardware complexity; high efficient multicast transmission; interconnected local mono-direction buses; local bus design; logical network; network coding; network on chip architecture; Encoding; Hardware; Local Bus; Network Coding; Network on Chip; throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Communications and Networking in China (CHINACOM), 2011 6th International ICST Conference on
  • Conference_Location
    Harbin
  • Print_ISBN
    978-1-4577-0100-9
  • Type

    conf

  • DOI
    10.1109/ChinaCom.2011.6158330
  • Filename
    6158330