A reliable 3 phi PWM strategy using a single-chip EPLD

A 3 phi PWM (three-phase pulsewidth-modulation) modulator, producing a reliable inverter bridge switching pattern, is described. The digital architecture for the modulator was developed using an EPLD CAD (erasable programmable logic device computer-aided design) system. A low-frequency ratio, synchronous-PWM switching pattern was adopted with fundamental frequency ranges varying from 0.60 Hz up to as high as 1 kHz. A square-wave reference waveform is used whereby the switching of each phase is limited to defined periods of the fundamental cycle. A linear relationship exists between the fundamental voltage and the modulation depth up to square-wave operation. These features allow the inverter bridge to be operated reliably with minimal electrical stresses being exerted on the inverter bridge power devices. The total harmonic distortion and fundamental percentage error are used to assess the modulator performance. The effects of minimum pulse widths on these performance factors are also demonstrated. Theoretical predictions of the PWM waveform harmonic content are verified with experimental results.<>