DocumentCode
3396565
Title
Parallel full-chip transient simulation at transistor level
Author
Peng, He ; Rouz, Khosro ; Borah, Manjit ; Cheng, Chung-Kuan
Author_Institution
CSE Dept., Univ. of California San Diego, La Jolla, CA
fYear
2008
fDate
27-29 Oct. 2008
Firstpage
239
Lastpage
242
Abstract
In this paper, we introduce an efficient parallel transistor level circuit simulation tool with SPICE-accuracy for full-chip circuit simulation. The new approach partitions the circuit based on circuit non-linearity and connectivity. Parallel domain decomposition technique is used to iteratively solve the different partitions of the circuit and ensure convergence. Orders of magnitude speedup over SPICE is observed for sets of large-scale design circuits.
Keywords
SPICE; VLSI; circuit simulation; integrated circuit design; transistors; SPICE-accuracy; VLSI circuit; circuit nonlinearity; circuit simulation; large-scale design circuits; parallel domain decomposition technique; parallel transistor level circuit simulation tool; transistor level; Circuit simulation; Circuit synthesis; Computational modeling; Concurrent computing; Convergence; Coupling circuits; Helium; Large-scale systems; Linear circuits; SPICE;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 2008 IEEE-EPEP
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-2873-1
Type
conf
DOI
10.1109/EPEP.2008.4675924
Filename
4675924
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