DocumentCode
3398310
Title
An all MOS neural-type cell
Author
Tsay, S.W. ; de Savigny, M. ; El-Leithy, N. ; Newcomb, R.
Author_Institution
Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
fYear
1991
fDate
14-17 May 1991
Firstpage
776
Abstract
An improved neural-type cell (NTC) using only MOS devices is presented. To yield neural-type pulse outputs, a load line is passed through the NTC hysteresis. The main contribution of the present work is the design of a nonlinear load line to improve the performance of the NTC. PSPICE simulations for a MAGIC IC layout using MOSIS parameters are given
Keywords
MOS integrated circuits; SPICE; circuit layout CAD; hysteresis; neural chips; MAGIC IC layout; MOS neural-type cell; MOSIS parameters; PSPICE simulations; hysteresis; neural-type pulse outputs; nonlinear load line; Biological system modeling; Educational institutions; Hysteresis; Laboratories; MOS devices; MOSFETs; Pulse circuits; Resistors; SPICE; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991., Proceedings of the 34th Midwest Symposium on
Conference_Location
Monterey, CA
Print_ISBN
0-7803-0620-1
Type
conf
DOI
10.1109/MWSCAS.1991.251998
Filename
251998
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