A statistical gate delay model for intra-chip and inter-chip variabilities

This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. Our model consists of a statistical transistor model and a gate-delay model. We present a modeling and extracting method of transistor characteristics for the intra-chip variability and the inter-chip variability. In the modeling of the intra-chip variability, it is important to consider the gate-size dependence by which the amount of intra-chip variation is affected. This effect is not captured in the statistical delay analyses reported so far. Our gate-delay model characterizes the statistical gate delay variation using a response surface method (RSM) according to the intra-chip and inter-chip variability of each transistor in a gate. We evaluate the accuracy of our model, and we show some simulated results of a circuit delay variation characterized by the measured variances of transistor currents.