A novel Delay Manager based on Digital DLL used to adjust the delay time of FPGA´s IO cell

A novel Delay Manager (DM) based on the Digital DLL designed to adjust the delay time of the FPGA´s IO port is proposed. The DDLL leverage the oversample mechanism to achieve high integration density and low power. A novel gear-shift component is utilized for both fast and precise locking in. To be adequate for digital data transmit, a new full-swing delay cell with good edge matching performance is used and the non-linearity is compensated with a nonlinear resister ladder DAC. Fabricated in a 65nm digital CMOS process, the simulation results show that the proposed architecture can operate at 50MHz with 256 non-invert delay-cell stages in line and the lock latency is one clock cycle. So the highest resolution of the Delay Manager can be as low as 78ps.