Challenges and limits for very low energy computation

This paper addresses the main challenges, limits and possible solutions for strongly reducing the energy per binary switching. The reduction of the stored energy in conventional logic can be done with a strong reduction in the applied bias using new physics and/or devices with sub-60mV/dec subthreshold swing, which is the limit of MOSFETs at 300K. The most promising ones, Tunnel FETs, use gate-controlled pin structures with carriers tunneling through the barrier and not flowing over. This paper addresses the main structures that have been proposed, using experiments or numerical simulations, for increasing Ion and reducing S for several decades of current.