Combining architecture exploration and a path to implementation to build a complete SoC design flow from system specification to RTL

Author

Dziri, M. Anouar ; Samet, Firaz ; Wagner, Flavio Rech ; Cesário, Wander O. ; Jerraya, Ahmed A.

Author_Institution

SLS Group, TIMA Lab., Grenoble, France

fYear

2003

fDate

21-24 Jan. 2003

Firstpage

219

Lastpage

224

Abstract

This paper presents a full System-on-Chip (SoC) design flow from system specification to RT-level. A new approach to obtain a full path to implementation for SoC design is proposed. This approach combines architecture design space exploration using the VCC design environment and system synthesis using the ROSES design flow, allowing a true and complete system level design flow. The experiment with a VDSL application shows a significant reduction of design time.

Keywords

circuit CAD; digital subscriber lines; high level synthesis; integrated circuit design; modems; system-on-chip; ROSES design methodology; RT-level specification; RTL synthesis; SoC design automation; SoC design flow; VCC design environment; VDSL framing; VDSL modem architecture specification; architectural design space exploration; system level design flow architecture; system-on-chip design; Application software; Computer architecture; Hardware; Laboratories; Laser sintering; Process design; Space exploration; System-level design; System-on-a-chip; Time to market;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific

Print_ISBN

0-7803-7659-5

Type

conf

DOI

10.1109/ASPDAC.2003.1195020

Filename

1195020