DocumentCode
3399109
Title
Ultra fast write speed, long refresh time, low power F-N operated volatile memory cell with stacked nanocrystalline Si film
Author
Shih-Jye Shen ; Chrong-Jung Lin ; Ching-Hsiang Hsu, C.
Author_Institution
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear
1996
fDate
8-11 Dec. 1996
Firstpage
515
Lastpage
518
Abstract
A new volatile memory structure with nanocrystalline Si layer and auxiliary floating polysilicon gate is reported. The charges are injected through tunnel oxide and nanocrystalline Si layer by FN tunneling and then stored in this stacked structure. The nanocrystalline Si layer with extended floating gate structure improves the limited charge storage volume, leads to a memory device with distinct threshold voltage window, and improves programming speed during FN operation. Based on the merit of low power F-N operation, high write speed, long refresh time and compatible CMOS process, this device is feasible for DRAM application.
Keywords
CMOS memory circuits; DRAM chips; integrated circuit measurement; integrated circuit reliability; nanostructured materials; plasma CVD; semiconductor thin films; tunnelling; 0.8 mum; DRAM application; Fowler-Nordheim tunneling; Si-SiO/sub 2/; auxiliary floating polysilicon gate; cell reliability; charge injection; compatible CMOS process; limited charge storage volume; long refresh time; low power Fowler-Nordheim operation; programming speed; stacked nanocrystalline Si film; threshold voltage window; tunnel oxide; ultra fast write speed; volatile memory cell; CMOS process; Fabrication; Nanoscale devices; Nanostructures; Nonvolatile memory; Plasma temperature; Random access memory; Semiconductor films; Silicon; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1996. IEDM '96., International
Conference_Location
San Francisco, CA, USA
ISSN
0163-1918
Print_ISBN
0-7803-3393-4
Type
conf
DOI
10.1109/IEDM.1996.553856
Filename
553856
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