Performance investigation of SRAM cells based on gate-all-around (GAA) Si nanowire transistor for ultra-low voltage applications

In this paper, the performance metrics (i.e., read and write margins, operation speed, power consumption) of 6T SRAM cell based on gate-all-around (GAA) Si nanowire transistor (SNWT) at 16nm technology node are investigated, as well as the impacts of device variations on GAA SNWT SRAM cells. The results indicate that GAA SNWT SRAM cells have larger read static noise margin, less power-delay product and better tolerance to process variations than planar bulk SRAM cells. And through cell ratio optimization, the GAA SNWT SRAM cells can satisfy the six-sigma (6σ) yield at V_DD=0.3V.