Propagation Delay Variations under Process Deviation in Driver Interconnect Load System

Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper provides a comprehensive overview of the types and sources of all aspects of process variations in driver -interconnect-load system. The primary sources of manufacturing variation include Deposition, Chemical Mechanical Planarization (CMP), Etching, Resolution Enhancement Technology (RET). Process variations manifest themselves as the uncertainties of circuit performance, such as delay, noise and power consumption. The impacts of these process variations on circuit delay are discussed in this paper for three different technologies i.e 130nm, 70nm and 45nm. The comparison of results between these three technologies shows that as device size shrinks the process variation becomes a dominant factor and subsequently increases the uncertainty of the delays.