A new parallel technique for design of decrement/increment and two´s complement circuits

Author

Hashemian, Reza ; Chen, Cheng P.

Author_Institution

Dept. of Electr. Eng., Northern Illinois Univ., De Kalb, IL, USA

fYear

1991

fDate

14-17 May 1991

Firstpage

887

Abstract

A novel design technique for the construction of a decrement/increment and two´s complement (DIT) circuit is presented. The technique is shown to be highly efficient of both in terms silicon area consumption and time. More interestingly, it is shown that the operation delay is almost independent of the word size, and hence the method is best used for high-density codes. Structurally, the circuit is made of two parallel paths: one for the input data and one for the generation of the control signal to be utilized for DIT operation through the data path. The circuit is designed and simulated for 64-bit word length using CMOS technology. For the worst-case situation, a 14.7 ns response time is reported

Keywords

CMOS integrated circuits; digital arithmetic; parallel architectures; 14.7 ns; 64 bits; CMOS technology; DIT operation; decrement/increment circuits; high-density codes; operation delay; parallel paths; parallel technique; response time; silicon area consumption; two´s complement circuits; word size; Arithmetic; CMOS logic circuits; CMOS technology; Delay; Design engineering; Hardware; Parallel processing; Search methods; Signal generators; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., Proceedings of the 34th Midwest Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-0620-1

Type

conf

DOI

10.1109/MWSCAS.1991.252070

Filename

252070