Prime Factor DFT parallel processor using wafer scale integration

A high speed, flexible, simple and regular Discrete Fourier Transform (DFT) Array Processor architecture based on the Prime Factor Algorithm (PFA) is presented in this paper. The array processor is based only on one type of VLSI cell and can compute an N point DFT in N clock cycles throughput when N is a composit number of prime numbers. The high throughput rate is achieved with only a small number of cells. With a special indexing scheme presented in this paper, this processor can use shift registers as the system memory so that minimum global control and addressing is achieved. This array processor architecture is also highly tolerant to both semiconductor processing yield and processor defects during run time. Thus, it can be manufactured in large quantity with VLSI technology on a single wafer and used in hazardus environments With these advantages, it is very attractive to satellite, military and commercial applications.