Title :
Optimizing InP HBT technology for 50 GHz clock-rate MSI circuits
Author :
Sokolich, M. ; Fields, C. ; Raghavan, G. ; Hitko, D.A. ; Lui, M. ; Docter, D.P. ; Brown, Y.K. ; Case, M.G. ; Kramer, A.R. ; Henige, J.A. ; Jensen, J.F.
Author_Institution :
HRL Lab., Malibu, CA, USA
Abstract :
Using experimental data and a sum of weighted RC time constant model we optimized AlInAs/GaInAs SHBT devices for minimum gate delay in a static divider. The best result obtained, a 55 GHz maximum clock rate, is to our knowledge the highest toggle rate reported to date. Comparable structures without critical base resistance optimization toggled at no more than 44 GHz. ft and fmax were observed to be only weak indicators of divider performance. The calculated maximum toggle rates obtained from the weighted RC time constant method agree reasonably well with experiment. The experiments and analysis lead to the conclusion that the dominant parasitic component in this regime of ultra-high speed HBT is the base resistance
Keywords :
III-V semiconductors; aluminium compounds; bipolar logic circuits; bipolar transistor circuits; frequency dividers; gallium arsenide; heterojunction bipolar transistors; indium compounds; integrated circuit modelling; semiconductor device models; very high speed integrated circuits; 44 to 55 GHz; 50 GHz clock-rate MSI circuits; AlInAs-GaInAs-InP; AlInAs/GaInAs SHBT devices; InP HBT technology; base resistance; critical base resistance optimization; dominant parasitic component; high speed logic; maximum toggle rates; minimum gate delay; static divider; toggle rate; ultra-high speed HBT; weighted RC time constant model; Capacitance; Circuits; Clocks; Contact resistance; Cutoff frequency; Delay effects; Geometry; Heterojunction bipolar transistors; Indium phosphide; Laboratories;
Conference_Titel :
Indium Phosphide and Related Materials, 1999. IPRM. 1999 Eleventh International Conference on
Conference_Location :
Davos
Print_ISBN :
0-7803-5562-8
DOI :
10.1109/ICIPRM.1999.773667
