• DocumentCode
    3401620
  • Title

    Incorporating manufacturing objectives into the semiconductor facility layout design process: A methodology and selected cases

  • Author

    Padillo, Jose M. ; Meyersdorf, Doron ; Reshef, Offer

  • Author_Institution
    TEFEN, Tempe, AZ, USA
  • fYear
    1997
  • fDate
    10-12 Sep 1997
  • Firstpage
    434
  • Lastpage
    439
  • Abstract
    This paper presents a methodology that provides a vehicle for the selection and ranking of layout design objectives. Moreover, the same methodology can be used to create a decision matrix to evaluate different alternative layouts under analysis. In this case, the methodology combines the ranking of the layout objectives with the relative performance of each layout alternative along each objective in order to recommend the “best” layout alternative. This structured methodology is based on a decision making tool known as the Analytical Hierarchy Process (AHP). These concepts are illustrated through several case studies taken from actual layout design projects in the semiconductor manufacturing industry
  • Keywords
    semiconductor device manufacture; Analytical Hierarchy Process; decision making tool; decision matrix; layout design; semiconductor manufacturing facility; Buildings; Fabrication; Floors; Manufacturing industries; Manufacturing processes; Process design; Production facilities; Productivity; Semiconductor device manufacture; Vehicles;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Semiconductor Manufacturing Conference and Workshop, 1997. IEEE/SEMI
  • Conference_Location
    Cambridge, MA
  • ISSN
    1078-8743
  • Print_ISBN
    0-7803-4050-7
  • Type

    conf

  • DOI
    10.1109/ASMC.1997.630776
  • Filename
    630776