Regular, area-time efficient carry-lookahead adders

For fast binary addition, a carry-lookahead (CLA) design is the obvious choice [OnAt83, BaJM831. However, the direct implementation of a CLA adder in VLSI faces some undesirable limitations. Either the design lacks regularity, thus increasing the design and implementation costs, or the interconnection wires are too long, thus causing area-time inefficiency and limits on the size of addition. Brent and Kung solved the regularity problem by reformulating the carry chain computation [BrKu82]. They showed that an n-bit addition can be performed in time O(log n), using area O(n log n) with maximum interconnection wire length o(n). In this paper, we give an alternative log n stage design which is nearly optimum with respect to regularity, area-time efficiency, and maximum interconnection wire length.