DocumentCode
3402666
Title
A DC-offset cancellation circuit for PGA in baseband communication
Author
Guanzhong Huang ; Yingjie Wu ; Chaoli Zhong ; Pingfen Lin
Author_Institution
Beijing Embedded Syst. Key Lab., Beijing Univ. of Technol., Beijing, China
fYear
2011
fDate
7-10 Aug. 2011
Firstpage
1
Lastpage
4
Abstract
This paper introduces a novel DC-offset cancellation circuit for PGA in baseband communication. The output DC-offset is reduced from over one hundred millivolts to less than 4mV in all cases with power dissipation of 6.6μW. At the same time, spurious-free dynamic range (SFDR) of PGA output is 51.4dB and the settling time of 63dB gain step switching is 372μs. The chip is fabricated in 0.18μm CMOS technology.
Keywords
CMOS integrated circuits; amplifiers; telecommunication equipment; CMOS technology; DC-offset cancellation circuit; PGA output; baseband communication; output DC-offset; power 6.6 muW; programmable-gain amplifier; size 0.18 mum; spurious-free dynamic range; time 372 mus; Bandwidth; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on
Conference_Location
Seoul
ISSN
1548-3746
Print_ISBN
978-1-61284-856-3
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2011.6026317
Filename
6026317
Link To Document