A fractional ΔΣ phase-to-digital converter for digitizing a phase-locked loop

This paper presents a circuit architecture for digitizing the VCO phase in a digital phase locked loop. The proposed architecture functions as a ΔΣ modulator in the phase domain to achieve noise shaping, and uses a Digital-To-Time Converter to achieve a fractional phase quantization step. The combination of the ΔΣ noise shaping and fractional quantization reduces quantization phase noise both in-band and out-of-band. Proof of concept is achieved using an event-driven VHDL model.