A high-speed and low-power pipelined binary search analog to digital converter

This paper presents a new analog to digital converter (ADC) architecture targeting ultra high speed and low power applications. The proposed ADC enables operation of SAR ADCs in a pipelined fashion trading latency for speed. Proposed ADC works based on binary search principle. The requirement for residue amplifier in conventional pipelined ADCs is eliminated by interleaved sampling of the analog input signal. Compared to an n-bit asynchronous SAR ADC, where the sampling rate is limited by n quantization delays and n DAC delays, the proposed ADC speed is only limited by two comparator delays and two DAC delays. A 6-bit 1 GS/s pipelined binary search (PBS) ADC was designed in 90nm CMOS process. Designed PBS ADC reaches a peak SNDR of 35.4dB consuming 3.8mW from a single 1.2V power supply.