Tutorial: The uncertain end to silicon

Summary form only given. As silicon technology moves progressively to ever smaller geometries, the uncertainties in the devices, due to atomic level imperfections and processing options become an ever larger factor in the design of systems-on-chip. The variabilities, mismatch and noise of 20nm and below process geometries dominate the design of these integrated circuits, affecting memory circuitry, analog blocks, digital logic and RF interfaces. We here discuss design practices to minimize systematic and random mismatch in memory blocks. We also discuss the emergence of Random Telegraph Noise in memory units. Design techniques for analog modules susceptible to mismatch and noise are considered, as are logic operation, guardbanding and operating stresses in the presence of these design uncertainties. RF operation is highly susceptible to phase noise issues, and limits, and mitigation methods are described. All these effects mean longer design cycles, and require operating safety margins that reduce the effectiveness of moving to the next process node. We investigate the question of whether it will be this type of process effect that will eventually stop silicon technology from advancing further.