Clock network design techniques for 3D ICs

3D die stacking is one of the most promising technology to overcome the traditional CMOS scaling limitations and clock network design is an important design activity to guarantee right operation and acceptable design characteristics of the target chips. This paper overviews and discusses recent research activities on the clock network design of TSV based 3D ICs. We overview a set of representative styles of clock network design for 3D ICs with an emphasis on their differences with that for 2D ICs, particularly discussing buffered 3D clock tree synthesis methods in detail. Then, research progress on the 3D clock network design considering temperature and/or process variation is discussed.