A graph-based silicon compiler for concurrent VLSI systems

A silicon compiler able to synthesize concurrent VLSI systems is described. This compiler differs from most existing silicon compilers as there is no target architecture, and yet results have shown that it performs reasonably well for a range of applications. It features a novel technique for control-step partitioning based on a precedence graph. Concurrency is detected and extracted from the input description in order to generate a fast implementation. The graph, which corresponds to a state diagram of the circuit, is further optimized using a simple rule-based approach. A controller able to control any number of concurrent processes, based on a synchronous token-passing mechanism, is generated. Control signals are submitted to two-level and multilevel logic minimization, and they can be implemented either as a programmable logic arrays (PLA) or with standard cells. The data path is generated as a netlist of technology-independent parameterized cells which are mapped into cells from a library by a module binder. The final layout is automatically generated by placement-and-routing programs