Unifying synchronous/asynchronous state machine synthesis

We present a design style and synthesis algorithm that encompasses both asynchronous and synchronous state machines. Our proposed design style not only supports generalized "burst-mode" multiple-input change asynchronous designs, but also allows the automatic synthesis of any synchronous Moore machine using only basic gates (and not state-holding elements). Moreover, the synthesis method covers many circuit styles in the range between burst-mode and fully synchronous. We can easily specify and synthesize sequential circuits which change state on both rising and falling clock edges, have multiple-phase clocks, etc., and mixed synchronous/asynchronous designs, subject only to setup and hold-time constraints. To demonstrate the effectiveness of the design style and the synthesis tool, we present a modified version of a previously published large practical controller design - the SCSI data transfer controller redesigned to improve performance and to eliminate preprocessing circuit for converting "level-sensitive" signals to "edge-sensitive" signals, often a cumbersome manual design process, by interfacing directly with "level-sensitive" signals.