Recent research in clock power saving with multi-bit flip-flops

In modern large-scale, high-speed digital integrated circuit (IC) design, power consumption of the clock network usually dominates the dynamic power of the chip due to its highest switching rate. To effectively minimize the power consumption of the clock network, recent studies have been investigating the usage of multi-bit flip-flops (MBFFs). This paper presents the advantages of applying MBFFs, introduces various MBFF design flows, surveys key techniques for design optimization with MBFFs, and provides some future research directions in clock power saving with MBFFs.