A low dead time variable CMOS delay for the Nuclear Weapons Identification System

Author

Puckett, B.S. ; Paulus, M.J. ; Mihalczo, J.T. ; Blalock, T.V.

Author_Institution

Instrum. & Controls Div., Oak Ridge Nat. Lab., TN, USA

Volume

1

fYear

1998

fDate

1998

Firstpage

468

Abstract

The architecture and performance of a new CMOS, low dead time, variable delay is described. This delay was developed to provide channel synchronization in the front-end electronics ASIC of the Nuclear Weapons Identification System (NWIS). The delay is variable over a 500 ns range in steps of less than 100 ps. Low dead time is achieved by using a switched parallel channel architecture. The delay channels are feedback stabilized by using a phase locked loop with a crystal reference. A prototype has been fabricated in the 1.2 μm AMI process

Keywords

CMOS integrated circuits; circuit feedback; circuit stability; delay circuits; digital phase locked loops; mixed analogue-digital integrated circuits; nuclear electronics; nuclear materials safeguards; synchronisation; weapons; AMI process; CMOS; Nuclear Weapons Identification System; channel synchronization; dead time; front-end ASIC; phase locked loop; switched parallel channel architecture; variable delay; Application specific integrated circuits; Delay effects; Delay systems; Feedback loop; Frequency synchronization; Laboratories; Neutrons; Nuclear weapons; Phase locked loops; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Nuclear Science Symposium, 1998. Conference Record. 1998 IEEE

Conference_Location

Toronto, Ont.

ISSN

1082-3654

Print_ISBN

0-7803-5021-9

Type

conf

DOI

10.1109/NSSMIC.1998.775184

Filename

775184