DocumentCode
3406982
Title
Fault dictionary compression and equivalence class computation for sequential circuits
Author
Ryan, P.G. ; Fuchs, W.K. ; Pomeranz, I.
Author_Institution
Intel Corp., Folsom, CA, USA
fYear
1993
fDate
7-11 Nov. 1993
Firstpage
508
Lastpage
511
Abstract
A new technique for creating small fault dictionaries for sequential circuits is presented, along with a hybrid combination of that new technique with another and performance improvements for a previously published technique. Seven techniques are compared and evaluated by their impact on dictionary size, fault simulation costs, and diagnostic resolution losses. The comparisons show that compact dictionaries with full resolution are computationally expensive, while small, inexpensive dictionaries almost always suffer a resolution loss. Measures of diagnostic resolution are described with an algorithm to approximate them in linear time. Experiments are presented for the ISCAS sequential benchmark circuits.
Keywords
fault diagnosis; ISCAS sequential benchmark circuits; computationally expensive; diagnostic resolution; diagnostic resolution losses; dictionary size; equivalence class computation; fault dictionaries; fault simulation costs; linear time; performance improvements; resolution loss; sequential circuits; Circuit faults; Circuit simulation; Cities and towns; Costs; Dictionaries; Electrical fault detection; Fault detection; Sequential circuits; Time measurement; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1993. ICCAD-93. Digest of Technical Papers., 1993 IEEE/ACM International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-4490-7
Type
conf
DOI
10.1109/ICCAD.1993.580105
Filename
580105
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