DocumentCode :
3407285
Title :
Boolean factorization using multiple-valued minimization
Author :
Liao, S. ; Devadas, S. ; Ghosh, A.
Author_Institution :
Dept. of EECS, MIT, Cambridge, MA, USA
fYear :
1993
fDate :
7-11 Nov. 1993
Firstpage :
606
Lastpage :
611
Abstract :
We show that the problem of factoring a sum-of-products representation of a logic function can be transformed into one of multiple-valued prime generation followed by branch-and-bound covering. We give a factorization method that generates potential Boolean factors by generating the primes of a multiple-valued function with an associated don´t-care set. A covering problem is solved wherein a set of primes with minimal cost is selected to obtain a Boolean factorization. This method can exploit Boolean identifiers in factorization such as a-a = a-a = a. Common factors across a set of Boolean functions can be identified by using multiple-output prime generation and covering. We show how all the kernels of an expression can be generated by generating the primes of a multiple-valued function. A covering step can be used to arrive at an algebraic factorization.
Keywords :
Boolean functions; Boolean factorization; Boolean functions; Boolean identifiers; algebraic factorization; associated don´t-care set; branch-and-bound; logic circuits; logic function; multiple-output prime generation; multiple-valued function; multiple-valued minimization; multiple-valued prime generation; sum-of-products representation; Boolean functions; Circuit synthesis; Circuit testing; Cost function; Delay; Kernel; Laboratories; Logic functions; Minimization; Optimization methods;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1993. ICCAD-93. Digest of Technical Papers., 1993 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-4490-7
Type :
conf
DOI :
10.1109/ICCAD.1993.580122
Filename :
580122
Link To Document :
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