Layout Uniformity: A metric for yield enhancement

Author

Lachkar, H. ; Rizzo, O. ; Portal, J.-M. ; Ginez, O.

Author_Institution

IM2NP, Marseille, France

fYear

2011

fDate

7-10 Aug. 2011

Firstpage

1

Lastpage

4

Abstract

The purpose of this paper is to study the relation between the layout features and the DFM flow effectiveness. First, a brief overview of the Design for Manufacturing (DfM) techniques used in yield aware RTL-to-GDSII design flow is given. This overview points out the possible relationship between the layout feature, i.e. density and uniformity and the DFM effectiveness. In order to validate layout uniformity as a first order metric to quantify layout sensitivity to DfM improvement, experiment is performed on industrial test case. The results of this experiment validate clearly that layout uniformity improvement correlates with CA and Lithography improvements.

Keywords

design for manufacture; integrated circuit layout; integrated circuit yield; lithography; DFM flow effectiveness; RTL-to-GDSII design flow; design for manufacturing; first order metric; industrial test case; layout features; layout uniformity; lithography; yield enhancement; Manufacturing; CA; CMP; Design for Manufacturability and Yield; OPC; Place & Route; SoCs; Uniformity;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on

Conference_Location

Seoul

ISSN

1548-3746

Print_ISBN

978-1-61284-856-3

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2011.6026576

Filename

6026576