Analog circuits sizing using bipartite graphs

This paper presents a new formalization of a hierarchical methodology for the sizing and biasing of analog IPs using bipartite directed acyclic graphs. This methodology allows to generate suitable sizing procedures that respect designer hypothesis and circuit topology. A library of simulator-based sizing and biasing operators using compact MOS models is used to ensure accurate sizing over different technologies. The bipartite graph formalization enables the designer to have sufficient insight on the sizing steps. Using this methodology with bipartite graphs, we sized and retargeted an amplifier from a 130nm to a 65nm process, then a low-power amplifier was migrated from an existing 180nm design to a 130nm technology.