ABR architecture and simulation for an input-buffered and per-VC queued ATM switch

Author

Bossardt, Matthias ; Park, Sueng-Yong ; Lockwood, John W. ; Kang, Sung-Mo

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

Volume

1

fYear

1998

fDate

1998

Firstpage

393

Abstract

This paper proposes an innovative concept, called virtual output queue, to support available bit rate (ABR) traffic on an input-buffered, per virtual circuit (VC) queued switch. This technique allows ABR models developed for output-buffered systems to be migrated to an input-buffered system. In order to evaluate the virtual output queue and to compare different ABR algorithms, a simulator of the ATM testbed at the University of Illinois has been enhanced with ABR functions. This paper provides simulation results for the input-buffered variation of the ERICA+ algorithm

Keywords

asynchronous transfer mode; buffer storage; computational complexity; digital simulation; queueing theory; telecommunication computing; telecommunication traffic; ABR algorithms; ABR architecture; ABR models; ABR traffic; ATM testbed; ERICA+ algorithm; University of Illinois; available bit rate; computation complexity; computer data transmission; fair-rate allocation algorithms; input-buffered ATM switch; input-buffered system; output-buffered systems; per virtual circuit queued switch; per-VC queued ATM switch; simulation results; virtual output queue; Algorithm design and analysis; Asynchronous transfer mode; Bandwidth; Communication switching; Computational modeling; Computer architecture; Feedback; Length measurement; Switches; Traffic control;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 1998. GLOBECOM 1998. The Bridge to Global Integration. IEEE

Conference_Location

Sydney,NSW

Print_ISBN

0-7803-4984-9

Type

conf

DOI

10.1109/GLOCOM.1998.775762

Filename

775762