A DRAM compiler for fully optimized memory instances

Author

Harling, Gord

fYear

2001

fDate

2001

Firstpage

3

Lastpage

8

Abstract

System-on-Chip (SoC) designs will soon be dominated by on-chip memory so there is an urgent need for customization of memory semiconductor intellectual property (SIP) to increase product differentiation. This paper describes a software compiler tool which can be used to customize DRAM memory arrays in both pure logic and merged logic processes. This compiler optimizes memory macrocells for speed, power, and area to obtain radically reduced area and power when compared to SRAM implementations. It can also create custom memories with very fine granularity

Keywords

DRAM chips; VLSI; application specific integrated circuits; cellular arrays; circuit CAD; circuit layout CAD; high level synthesis; integrated circuit design; random-access storage; timing; DRAM compiler; DRAM memory array customisation; EDA tool; SoC designs; VHDL netlists; Verilog netlists; area; assembler module; custom memories; document generator; memory macrocells optimisation; memory semiconductor intellectual property; merged logic processes; netlister; on-chip memory; power; pure logic processes; software compiler tool; speed; system-on-chip designs; timing; very fine granularity; Bandwidth; Integrated circuit manufacture; Intellectual property; Logic arrays; Macrocell networks; Optimizing compilers; Random access memory; SRAM chips; System-on-a-chip; Tiles;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, IEEE International Workshop on, 2001.

Conference_Location

San Jose, CA

Print_ISBN

0-7695-1242-9

Type

conf

DOI

10.1109/MTDT.2001.945221

Filename

945221