Low voltage and low leakage flip-flops based on transmission gate in nanometer CMOS processes

Scaling supply voltage is an effective technique to achieve low energy delay product (EDP). This paper presents low voltage and low leakage flip-flops using dual-threshold CMOS (low threshold and ultra high threshold) to reduce leakage power. Four flip-flops based on transmission gates are investigated from 0.3V to 1.1V in term of EDP. The simulation results show that lowering supply voltage is advantageous, especially in low voltage region (800mv-900mv) at 45nm CMOS technology, which yields the best EDP. The proposed flip-flop achieves considerable leakage reductions.